In general, when signals are transmitted and received to and from two LSIs operating with different amounts of power supply voltage, voltage levels of the signals handled by the two LSIs differ from each other. Therefore, the LSI with the low power supply voltage is provided with a level converter that converts the voltage level of the signal, which is be output to the LSI with the higher power supply voltage, into the higher power supply voltage from the low power supply voltage.
FIG. 1 is a diagram illustrating an example of a circuit configuration of a level converter. A level converter 100 illustrated in FIG. 1 includes a level conversion circuit 102, an inverters 104, 106, and 108, and a transistor 110 for power supply sequence control.
In the level converter 100, the level conversion circuit 102, which is provided between a high voltage power supply line HVDD and a ground power supply line GND, receives a non-inverted signal and an inverted signal of an input signal, which is supplied to an input node INPUT through the inverters 104 and 106, as a differential input. At this time, the input signal has an H level (“1”) for a power supply voltage level LVL of a low voltage power supply line LVDD and an L level (“0”) for a ground level GVL of the ground power supply line GND. The power supply voltage level LVL of the low voltage power supply line LVDD is lower than a power supply voltage level HVL output from the high voltage power supply line HVDD.
The level conversion circuit 102 converts the input signal into a signal of which the power supply voltage level HVL of the high voltage power supply line HVDD is the H level (“1”) and of which a ground level GVL is the L level (“0”) and outputs the signal of which the voltage level corresponding to each logic level is converted. An output node LVOUT of the level conversion circuit 102 is coupled to the input node of the inverter 108. The inverter 108 inverts the output signal from the output node LVOUT of the level conversion circuit 102 and supplies the inversed signal as an output signal of the level converter 100 to an output node OUTPUT.
The level converter 100 is coupled to the high voltage power supply line HVDD to which a power supply voltage level HVL is supplied from the high voltage power supply and to the low voltage power supply line LVDD to which a power supply voltage level LHL is supplied from the low voltage power supply and operates based on those power supply voltages. The level converter 100 is desired to operate normally regardless the sequence of the above-described two power supplies to be supplied. That is, the level converter 100 is desired to be power supply sequence free.
To be power supply sequence free, the level converter 100 includes the transistor 110 for power supply sequence control. The transistor 110 is, for example, a P-channel transistor provided between the high voltage power supply line HVDD and the output node LVOUT of the level conversion circuit 102. A gate of the transistor 110 is coupled to the low voltage power supply line LVDD.
FIGS. 2A and 2B are timing charts illustrating an operation of the level converter 100 at a time of supplying power. When the high voltage power supply and the low voltage power supply are supplied, the high voltage power supply is turned on before the low voltage power supply. During a power-on period T1 in which the low voltage power supply is turned off while the high voltage power supply is turned on, the transistor 110 is turned on because the input signal of the ground level GVL (L level) is input into the gate. Therefore, as illustrated in FIG. 2A, the transistor 110 electrically couples the output node LVOUT of the level conversion circuit 102 to the high voltage power supply line HVDD and fixes the voltage level of the output node LVOUT to the power supply voltage level HVL of the high voltage power supply line HVDD. Due to this, the voltage level of the output signal of the output node OUTPUT is fixed to the ground level GVL.
Accordingly, regarding the level converter 100, even when the low voltage power supply is turned off while the high voltage power supply is turned on, a signal of which the voltage level is unstable is input from the output node OUTPUT into a latter stage circuit with the identical high voltage power supply as an operation power supply voltage. This prevents the latter stage circuit from malfunctioning and a through current from being generated in the latter stage circuit.
Japanese Laid-open Patent Publication No. 2004-356779 discloses a technique for preventing the through current from being generated in an output driver by putting a transistor, which has the output driver to which an output signal from a level shifter is supplied, in a cut-off state while the low voltage power supply is not operating.
On the other hand, in a normal operation period T2 of the level converter 100 where both the high voltage power supply and the low voltage power supply are turned on, the signal of the power supply voltage level LVL (H level) is input into the gate of the transistor 110 from the low voltage power supply line LVDD. Due to this, although the level converter 100 tries to turn off the transistor 110, the voltage level of the source of the transistor 110 is the power supply voltage level HVL of the high voltage power supply line HVDD, and the voltage level of the source of the transistor 110 indicates a potential between the voltage level and the ground level. Thus, the transistor 110 may not be completely turned off. Therefore, the transistor 110 may not completely separate the output node LVOUT of the level conversion circuit 102 from the high voltage power supply line HVDD.
As illustrated in FIG. 1, in the normal operation period T2, regarding the level conversion circuit 102, a through current ID flows between the high voltage power supply line HVDD and the ground power supply line GND through the transistors 110 and 112 at a timing when the transistor 112 provided between the output node LVOUT and the ground power supply line GND is turned on. Regarding the level converter 100, consumption current increases due to the through current ID. As a result, there is a problem that the consumption power increases.
For example, as illustrated in FIG. 2B when the power supply voltage level of the high voltage power supply line HVDD is 1.50V and when the power supply voltage level of the low voltage power supply line LVDD is 0.85V, the voltage level of the gate of the transistor 110 indicates an intermediate potential that is as high as half the voltage level of the source. Due to this, the transistor 110 is not completely turned off (HVL=1.50V, LVL=0.85V). Therefore, when the voltage level of the input signal is the H level (LVL), the transistor 112 is turned on. Thus, the through current ID flows. Although the signal of the H level (HVL) is output from the output node, the voltage level of the output node LVOUT does not reach 0V (ground level GVL) due to influence of a voltage decrease generated in the transistor 110 caused by the through current ID.
In general, the LSI includes many output terminals.
The level converter 100 illustrated in FIG. 1 is provided for each of the output terminals. That is, since the number of level converters 100 is similar to the number of output terminals of the LSI, the through current of the whole LSI caused by the level converter 100 increases according to the number of output terminals of the LSI. Therefore, even if the through current value of a single level converter 100 is small, the through current of the whole LSI increases. This causes an increase of the consumption power of the LSI. Since the number of output terminals of the LSI has increased in recent years, the increase of the consumption power of the LSI caused by the through current of the level converter 100 has been a large obstacle in power saving of the whole LSI.
In the above-described case, if the gate length of the transistor 110 is longer than the gate length of each transistor included in the level conversion circuit 102, the value of the current flowing in the transistor 110 may be reduced by increasing the resistance value of the transistor 110 in the above-described normal operation period T2. In this case, however, the through current may not be eliminated.